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Off topic: 茶馆 : 所有"无关紧要的"话题
Thread poster: xxxchance
ysun  Identity Verified
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漫谈历史 Feb 19, 2008

Wenjer Leuschel wrote:

可惜,历史不是基于假设的问题建构起来的,而是由真正发生的事件和事件中人们的处理方式,以及各方势力平衡的结果决定的。即使我们在台湾由于受到高压统治的经验,对“军头”没有好感,但文化大革命当时的中国情况,也许由一位像林彪那样的军头收拾残局,会比持续动乱六、七年下去好许多。


你这话有一定道理。如果1976年没有叶帅鼎力协助华国锋粉碎四人帮,很难说还要乱多久。若没有叶帅鼎力协助,华国锋是无能为力的,“闲居”的“总设计师”更无能为力。后来, "CEO” 把总设计师给请出来,总设计师却把 "CEO” 给请下台。

如果基于假设重新构建一下历史,假如当时 "CEO” 没下台,现在将是怎么个状况呢?说不定未必会比现在差,至少贪官污吏会少一些。发展也许会慢一些、稳一些,但贫富差异可能不会这么大,物价可能不会涨得这么快。这就是为什么很多老百姓还在怀念毛主席的原因。不过,假设毕竟是假设,各种结局都有可能。无论如何,历史的潮流是不可阻挡的,不是以个别人的意志为转移的,也许会像黄河那样拐上一个大弯,但最终还将流向大海。不乱不治,乱到一定时候就有人出来治。陈良宇事件就是一例。


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xxxchance
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放肆的假设,你不想回国了 :D Feb 19, 2008

Yueyin Sun wrote:

如果基于假设重新构建一下历史,假如当时 "CEO” 没下台,现在将是怎么个状况呢?说不定未必会比现在差,至少贪官污吏会少一些。发展也许会慢一些、稳一些,但贫富差异可能不会这么大,物价可能不会涨得这么快。这就是为什么很多老百姓还在怀念毛主席的原因。不过,假设毕竟是假设,各种结局都有可能。无论如何,历史的潮流是不可阻挡的,不是以个别人的意志为转移的,也许会像黄河那样拐上一个大弯,但最终还将流向大海。不乱不治,乱到一定时候就有人出来治。陈良宇事件就是一例。


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ysun  Identity Verified
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我若想回国会有签证但没钱 Feb 19, 2008


chance wrote:

放肆的假设,你不想回国了


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xxxchance
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签证也涨价了 Feb 19, 2008



Yueyin Sun wrote:
我若想回国会有签证但没钱

chance wrote:

放肆的假设,你不想回国了


[Edited at 2008-02-19 15:07]


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ysun  Identity Verified
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外交对等原则 Feb 19, 2008

双方就比着涨吧,就苦了老百姓了。:-(
chance wrote:

签证也涨价了



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Wenjer Leuschel  Identity Verified
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回到前头的主题 Feb 19, 2008

历史虽然不能倒流,我个人却比较喜欢稍微迟缓稳重的发展,不论个人或社会整体。由于有了总设计师把CEO请下台的历史,才会有今天贫富差距极巨的局面,为将来埋下很深的不安定因素。

水是往下流的,人是趋于利的;所以,饮酖止渴的作为会不断发生。这也许是我们在思想上属于左的人的看法,但将来的发展肯定会证实我们这种看法。


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Wenjer Leuschel  Identity Verified
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换个题目 Feb 20, 2008

Steve,

我记得你的专业是Double E,所以特别请教你一个问题。

计算机里不可或缺的“节拍”,是利用一个一定周期的振荡器产生两个相同周期的sine和cosine的振荡输出;由于sine和cosine的相位差恰巧是90°,因此这两个振荡的“和”只在周期1/4和3/4的时点上形成清楚的节拍。我的问题是,要产生这两个相位差恰巧是90°的振荡,振荡器的振荡必须经过错位调制;那么,振荡器的振荡周期会如何影响错位调制的线路呢?In short, how to achieve two outputs that are exactly 90° out of phase with the same oscillator? In which way would the frequency of the oscillator determine the generation and routing of these two outputs?

Could you point out some online references for me? Thank you in advance!

- Wenjer


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wherestip  Identity Verified
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Clocks Feb 20, 2008

Wenjer Leuschel wrote:

Steve,

我记得你的专业是Double E,所以特别请教你一个问题。

计算机里不可或缺的“节拍”,是利用一个一定周期的振荡器产生两个相同周期的sine和cosine的振荡输出;由于sine和cosine的相位差恰巧是90°,因此这两个振荡的“和”只在周期1/4和3/4的时点上形成清楚的节拍。我的问题是,要产生这两个相位差恰巧是90°的振荡,振荡器的振荡必须经过错位调制;那么,振荡器的振荡周期会如何影响错位调制的线路呢?In short, how to achieve two outputs that are exactly 90° out of phase with the same oscillator? In which way would the frequency of the oscillator determine the generation and routing of these two outputs?

Could you point out some online references for me? Thank you in advance!

- Wenjer


Wenjer,

I thought this thread was for some easy and relaxing topics, 即茶馆里谈的

Anyway, most of the chip designs we engage in only use a system clock and an inverted clock, i.e. 180 degrees out of phase. Nowadays with higher and higher frequencies, the system clock is first distributed throughout the chip using a clock grid. Clock splitters are then used to generate the clocks and their complementary inverted clocks which are then connected to the flip-flops (or latches as we call them). The use of a passive 90 degree delay book would be sufficient for places where such a phase shift is required, but that situation would be very rare and moreover very localized, not to mention the 90 degree phase shift wouldn't be very precise.

So I'm thinking you are referring to board designs that might need to utilize clocks that are 90 degrees out of phase. I would think the most common way to generate such clocks would be to use phase-locked-loops or DPLLs. Here are two patents that talk about some 90 degree out-of-phase clock generation techniques. You can see detailed explanation of the patents by clicking on the tabs at the top: abstract, claims, description, full text, etc.

http://www.patentstorm.us/patents/5399995.html

http://www.patentstorm.us/patents/5546434-claims.html

I'm not sure I understood your question completely. It would help to clarify the application. Of course that doesn't mean I would have a good answer for you.



[Edited at 2008-02-20 13:57]


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wherestip  Identity Verified
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A little more on clocks Feb 20, 2008

Theoretically, one can generate two clocks that are 90 degrees out of phase based on a square wave that is running at twice the frequency of the output clocks needed.

Use a clock divider to divide the original square wave. This would be clock A.

Invert the original square wave, and then divide the inverted waveform by two. This would be clock B.

Clock B would lag clock A by 90 degrees.


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xxxchance
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这叫搬起石头砸自己的脚 Feb 20, 2008

西方有人为追求利润,把那些高精网络技术卖给中国政府去控制网民,现在又称受到来自中国的强劲攻击,呵呵

http://www.rfi.fr/actucn/articles/098/article_5928.asp


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wherestip  Identity Verified
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Phase Locked Loops Feb 20, 2008

http://en.wikipedia.org/wiki/Phase-locked_loop

http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

Wenjer,

If the requirement of your application needs two clocks that are precisely 90 degrees out of phase, IMO the most likely solution is by using a phase locked loop, which is a specialty all in itself. The basic idea is the original input reference clock and the feedback at the input port to the PLL automatically synchronize to each other. Therefore one fiddles with the feedback circuitry, and taps off the appropriate point to get the desired output characteristics.

Anyway, that in a nutshell is about all I know about phase locked loops. Anyone with more knowledge in this area is certainly welcome to pipe up and help Wenjer with his question.



[Edited at 2008-02-21 02:30]


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wherestip  Identity Verified
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Actually Feb 20, 2008

Wenjer,

In principle, combine my last two posts together, and you get two clocks that are 90 degrees out of phase.

Use a phase locked loop to generate a 2X clock. Divide the output by 2 to get clock A. Additionally, invert the output, then divide by 2 to get clock B. As I said, clock B would lag clock A by 90 degrees.

That's a simplistic scheme. Some deskewing techniques might need to be applied to account for the delays in the logic. The schemes suggested in the two above patents are bound to be more elaborate and should generate clocks with less jitter and more precision.

I'm not sure if I'm answering your question. Or am I completely missing the point? Excuse me if it's the latter


~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*

p.s. Here's another link where there's a discussion of how to generate freq. multiples of a sine wave, FWIW. The 1st post is the same as what I was suggesting, while the last is basically a variation of it. The other two posts seem to be talking about an analog approach that derives the sine and cosine outputs from the feedback circuitry of a PLL as I mentioned in my last post.

http://www.dsprelated.com/showmessage/23638/1.php



[Edited at 2008-02-20 18:11]


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wherestip  Identity Verified
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Summing a sine and cosine to generate a clock Feb 20, 2008

Wenjer Leuschel wrote:


计算机里不可或缺的“节拍”,是利用一个一定周期的振荡器产生两个相同周期的sine和cosine的振荡输出;由于sine和cosine的相位差恰巧是90°,因此这两个振荡的“和”只在周期1/4和3/4的时点上形成清楚的节拍。



Wenjer,

This morning I didn't quite understand what you were referring to by the above description. Now that I go over what you described more carefully, I kind of question this approach of generating a system clock. If I understand you correctly, you're saying a system clock is generated by superimposing or summing up a sine and a cosine signal, thereby deriving the rising edge at the 1/4 point and the falling edge at the 3/4 point.

I actually never heard of this. There are differential clocks that kind of work in a similar fashion, but the two signals are 180 degrees out of phase, and the plus signal is added to the inverse of the minus therefore cancelling out any potential noise. I asked a few colleagues of mine, and they also said they haven't heard of this clocking scheme before either.

Am I wrong about this?

Is this a clock generating scheme suggested by a patent you are translating? I wonder what the advantage of such a scheme would be. It certainly seems to be more trouble than it's worth, necessitating the production of a sine wave and its corresponding cosine with much precision ... Just my opinion.



[Edited at 2008-02-20 22:16]


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Wenjer Leuschel  Identity Verified
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Local time: 09:11
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Great! Feb 21, 2008

wherestip wrote:

Wenjer,

Combine my last two posts together, and you get two clocks that are 90 degrees out of phase.

Use a phase locked loop to generate a 2X clock. Divide the output by 2 to get clock A. Additionally, invert the output, then divide by 2 to get clock B. As I said, clock B would lag clock A by 90 degrees.

I'm not sure if I'm answering your question. Or am I completely missing the point? Excuse me if it's the latter


Steve,

Thank you very much! Now I know the trick of generating 2 clocks that are 90° out of phase with one oscillator. The PLL and the inversion after doubling help. That was what I want to know about "routing" from the one and the same oscillator. Many thanks again!

- Wenjer


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Wenjer Leuschel  Identity Verified
Taiwan
Local time: 09:11
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Just an idea Feb 21, 2008

Steve,

No, I am not translating anything like that. I just want to know what if a system clock is composed of an oscillator and the same oscillator with two outputs 90° out of phase to have sine and cosine combined at the same time. The idea is, sine and cosine would cancell each other at 90° and 270° and thus produce a distinct drop at those points, while during other times, the oscillation is either "high" or "low." The precision is a problem, I know.

- Wenjer

wherestip wrote:

Wenjer,

This morning I didn't quite understand what you were referring to by the above description. Now that I go over what you described more carefully, I kind of question this approach of generating a system clock. If I understand you correctly, you're saying a system clock is generated by superimposing or summing up a sine and a cosine signal, thereby deriving the rising edge at the 1/4 point and the falling edge at the 3/4 point.

I actually never heard of this. There are differential clocks that kind of work in a similar fashion, but the two signals are 180 degrees out of phase, and the plus signal is added to the inverse of the minus therefore cancelling out any potential noise. I asked a few colleagues of mine, and they also said they haven't heard of this clocking scheme before either.

Am I wrong about this?

Is this a clock generating scheme suggested by a patent you are translating? I wonder what the advantage of such a scheme would be. It certainly seems to be more trouble than it's worth, necessitating the production of a sine wave and its corresponding cosine with much precision ... Just my opinion.


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