Login or register (free and only takes a few minutes) to participate in this question.You will also have access to many other tools and opportunities designed for those who have language-related jobs (or are passionate about them). Participation is free and the site has a strict confidentiality policy. English to Italian translations [PRO] Tech/Engineering - Computers: Hardware / DIMM DDR2 | | English term or phrase: traces listed | Gentili utenti
Non riesco a capire questo testo, mi aiutereste a trovare una soluzione? "The spacing adjacent to traces listed in this table is a minimum value.
Additional space to other traces can be added and not count as a failure."
Argomento: memorie DIMM DDR2
Contesto:
Options for routing on boards with 4-mil dielectric and on boards with 4.5-mil dielectric are
mutually exclusive. Do not use a combination of these checklist items.
Notes: The four unbuffered DIMM layout rules apply to BTX and non-BTX designs.
The spacing adjacent to traces listed in this table is a minimum value.
Additional space to other traces can be added and not count as a failure.
A two-DIMM design can also be implemented using the four-DIMM design
guidelines.
Table 3. Checklist for Four Unbuffered DDR2 DI M M s
Layout
General Rules The DIMM placement should be interleaved (DIMM_A0, DIMM_B0,
DIMM_A1, DIMM_B1).
Explanation
Channel B should be routed on the top signal layer in the bus channel
segments.
Channel A should be routed on the bottom signal layer in the bus
channel segments.
The part of the DDR net that is routed with a narrow trace to break out
of the processor pin field should be shorter than 500 mils.
The traces in the DIMM channel are routed with 6-mil spacing to
other traces but can be routed with as little as 5-mil spacing for a total
of 100 mils of length.
All DDR nets in the processor breakout area and the DIMM channel
are at a minimum 4 mils wide.
All DDR nets in the processor breakout area should maintain at least
6-mil spacing to other nets in the breakout region. If three traces are
routed between two vias, the trace spacing can briefly reduce to
4 mils.
In the processor breakout area, the memory CLK and DQS trace
differential spacing is no more than 6 mils. |
|  Andrea PiuKudoZ activityQuestions: 86 (none open) Answers: 100 Italy
| | Local time: 20:17
|
| | Italian translation:tracce elencate | Explanation: salve.
dovrebbe essere così.
spero di averla aiutata |
| Selected response from: Stefano Iul Italy Local time: 20:17
| Grading comment Grazie comunque del contributo 4 KudoZ points were awarded for this answer |
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