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flanco de reloj

English translation: clock edge

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18:52 Sep 20, 2007
Spanish to English translations [PRO]
Tech/Engineering - Science (general)
Spanish term or phrase: flanco de reloj
Here are a couple of examples - thanks in advance

lo cual hace que en cuanto una es controlada, no controla la siguent hasta el siguiente **flanco de reloj** en el cual el sistema pasa a la siguiente variable, la variable anterior es corrompida o señala un error en el sistema,

todas las variables se analizarían en el mismo **flanco de reloj**, en cada **flanco**, y detectaría el error en nanosegundo
Ronnie McKee
Spain
Local time: 22:37
English translation:clock edge
Explanation:
From http://www.tek.com/Measurement/cgi-bin/framed.pl?Document=/M...

Adquisición sincrónica de alta velocidad: La arquitectura de sobremuestreo digital asincrónico permite a la Serie TLA 700 soportar la adquisición sincrónica de alta velocidad en todos los canales. El detector de **flanco de reloj** busca entre los datos de sobremuestreo los flancos de la señal que coinciden con la definición de la configuración del reloj. Sobre la base de especificaciones de establecimiento y retención definidas por el usuario, se selecciona en la corriente de datos muestreados de todos los demás canales una muestra específica, relativa a la temporización de los flancos del reloj. Las muestras seleccionadas se almacenan luego, con marcas de tiempo, como datos sincrónicos de la memoria de adquisición primaria y se descartan todas las demás muestras. Esta ubicación precisa de los puntos de muestreo, junto con las nuevas sondas de gran ancho de banda, permite a la Serie TLA 700 proporcionar adquisiciones de estado a 200 MHz con una ventana de establecimiento y retención muy pequeña, usualmente del orden de 2 ns en todos los canales.

Here is the corresponding text in English (same website):
High-Speed Synchronous Acquisition: The asynchronous digital oversampling architecture enables the TLA 700 Series to support high-speed synchronous acquisition on all channels. The **clock edge** detector searches through the oversampled data looking for clock edges that match the clocking setup definition. Based on user-defined setup-and-hold specifications, a specific sample is then selected out of the sampled data stream of all other channels, relative to the timing of the clock edge. The selected samples are then stored, with timestamps, as synchronous data in the primary acquisition memory and all other samples are discarded. This precise sample point placement, together with new high-bandwidth probes, enables the TLA 700 Series to provide 200 MHz state acquisition with a very small setup-and-hold window, typically about 2 ns across all channels.
Selected response from:

eesegura
Local time: 15:37
Grading comment
4 KudoZ points were awarded for this answer

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Summary of answers provided
3 +4clock edge
eesegura
4clock flank
R-i-c-h-a-r-d
2 -1flip flop edgeAlicia Villegas


Discussion entries: 1





  

Answers


14 mins   confidence: Answerer confidence 4/5Answerer confidence 4/5
clock flank


Explanation:
It's used for system timing in computer terms I believe :)

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Note added at 16 mins (2007-09-20 19:09:38 GMT)
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Maybe some these links are useful:

A suggested solution is to require that all signals (except the clock) are constant over the clock flank. This can be achieved by requiring that inputs ...
www.eda.org/ieee-1850/hm/0030.html

positive or negative clock flank to activate the following standard clock register means ... large we must change the clock flank of the second register. ...
www.physto.se/~ker/prr/timing.PDF

in the output generation counter to synchronise output clock flanks to. the clock flanks of the reference. Output generation counter: The output generation ...
http://ieeexplore.ieee.org/iel5/2220/27876/01244149.pdf?arnu...

etc...

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Note added at 19 mins (2007-09-20 19:12:00 GMT)
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Here's my Glossary entry:
http://www.proz.com/?sp=gloss/term&id=4262892

I came across this term during an computing translation a while back.

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Note added at 35 mins (2007-09-20 19:27:42 GMT)
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From outta space - bizarre I agree.
Note that it's not 'CLOCK SIDE' (As suggested by another colleague in the PT-EN pair), now that's just being silly!

R-i-c-h-a-r-d
Brazil
Local time: 17:37
Works in field
Native speaker of: Native in EnglishEnglish
Notes to answerer
Asker: Interesting, I didn't even try to search for "clock flank". It sounds so far fetched. But I guess its not!


Peer comments on this answer (and responses from the answerer)
neutral  Robin Levey: It's not wrong, but no self-respecting anglophone engineer would refer to 'flanks' in this context.
1 hr
Login to enter a peer comment (or grade)

1 hr   confidence: Answerer confidence 3/5Answerer confidence 3/5 peer agreement (net): +4
clock edge


Explanation:
From http://www.tek.com/Measurement/cgi-bin/framed.pl?Document=/M...

Adquisición sincrónica de alta velocidad: La arquitectura de sobremuestreo digital asincrónico permite a la Serie TLA 700 soportar la adquisición sincrónica de alta velocidad en todos los canales. El detector de **flanco de reloj** busca entre los datos de sobremuestreo los flancos de la señal que coinciden con la definición de la configuración del reloj. Sobre la base de especificaciones de establecimiento y retención definidas por el usuario, se selecciona en la corriente de datos muestreados de todos los demás canales una muestra específica, relativa a la temporización de los flancos del reloj. Las muestras seleccionadas se almacenan luego, con marcas de tiempo, como datos sincrónicos de la memoria de adquisición primaria y se descartan todas las demás muestras. Esta ubicación precisa de los puntos de muestreo, junto con las nuevas sondas de gran ancho de banda, permite a la Serie TLA 700 proporcionar adquisiciones de estado a 200 MHz con una ventana de establecimiento y retención muy pequeña, usualmente del orden de 2 ns en todos los canales.

Here is the corresponding text in English (same website):
High-Speed Synchronous Acquisition: The asynchronous digital oversampling architecture enables the TLA 700 Series to support high-speed synchronous acquisition on all channels. The **clock edge** detector searches through the oversampled data looking for clock edges that match the clocking setup definition. Based on user-defined setup-and-hold specifications, a specific sample is then selected out of the sampled data stream of all other channels, relative to the timing of the clock edge. The selected samples are then stored, with timestamps, as synchronous data in the primary acquisition memory and all other samples are discarded. This precise sample point placement, together with new high-bandwidth probes, enables the TLA 700 Series to provide 200 MHz state acquisition with a very small setup-and-hold window, typically about 2 ns across all channels.



    Reference: http://www.tek.com/Measurement/cgi-bin/framed.pl?Document=/M...
eesegura
Local time: 15:37
Works in field
Native speaker of: Native in EnglishEnglish
PRO pts in category: 4

Peer comments on this answer (and responses from the answerer)
agree  Robin Levey: Cierto! Siempre se dice 'edge' (leading edge, trailing edge, etc.) y jamás 'flank'.
34 mins
  -> ¡Muchas gracias, mediamatrix!

agree  bigedsenior
7 hrs
  -> Thank you, bigedsenior!

agree  R-i-c-h-a-r-d: edge it is :)
8 hrs
  -> Thank you, Richard!

agree  Lanna Rustage: AGREE, DEFINITELY
11 hrs
  -> Thank you, lannarusta!
Login to enter a peer comment (or grade)

28 mins   confidence: Answerer confidence 2/5Answerer confidence 2/5 peer agreement (net): -1
flip flop edge


Explanation:
ver web

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Note added at 2 horas (2007-09-20 21:18:47 GMT)
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thanks.


    Reference: http://es.wikipedia.org/wiki/Biestable
    Reference: http://en.wikipedia.org/wiki/Flip-flop_%28electronics%29
Alicia Villegas
Argentina
Native speaker of: Native in SpanishSpanish

Peer comments on this answer (and responses from the answerer)
disagree  Robin Levey: 'flip-flop' is wrong - 'clock edge' is correct.
1 hr
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