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 Member since Mar '08
Working languages: Japanese to English
|  Lauren Barrett
20 yrs in translation, MIT graduate
MA, United States Local time: 08:01 EST (GMT-5)
Native in: English  | | |
Freelancer,  Verified member | | Translation | | Specializes in: | | Patents | Chemistry; Chem Sci/Eng | | Materials (Plastics, Ceramics, etc.) | Telecom(munications) | | Electronics / Elect Eng | Medical: Pharmaceuticals | | Mechanics / Mech Engineering |
| Also works in: | | Automation & Robotics | Automotive / Cars & Trucks | | Biology (-tech,-chem,micro-) | Computers (general) | | Computers: Hardware | Energy / Power Generation | | Engineering (general) | Law: Patents, Trademarks, Copyright | | Manufacturing | Medical: Instruments | | Metallurgy / Casting | Mining & Minerals / Gems | | Nuclear Eng/Sci | Petroleum Eng/Sci | | Science (general) |
More Less | | Questions asked: 5 | Sample translations submitted: 1 Japanese to English: Vertical MOSFET
General field: Law/Patents
Detailed field: Materials (Plastics, Ceramics, etc.) | Source text - Japanese
【要約】
【課題】オン抵抗を著しく下げることが可能でしかも製
造の容易な縦型ＭＯＳＦＥＴを提供する。
【解決手段】ｎ ドレイン層１１上のｎドリフト領域１
２の表面層にｐウェル領域１４が形成され、そのｐウェ
ル領域１４内にｎソース領域１５が形成され、ｎソース
領域１５とｎドリフト領域１２とに挟まれたｐウェル領
域１４の表面上にゲート絶縁膜１６を介してゲート電極
１７が設けられ、ｎソース領域１５とｐウェル領域１４
との表面に共通に接触するソース電極１８が設けられた
縦型ＭＯＳＦＥＴにおいて、ｎドリフト領域１２の不純
物濃度分布を深さ方向に次第に高くなる直線的な分布と
し、ｐウェル領域１４の表面からトレンチ２２を掘り下
げ、そのトレンチ２２内に厚い絶縁膜２０を介してソー
ス電極と短絡される多結晶シリコン２１を埋める。
【特許請求の範囲】
【請求項１】高濃度の第一導電型基板上に形成された低
濃度の第一導電型ドリフト領域と、その表面層に選択的
に形成された第二導電型ウェル領域と、その第二導電型
ウェル領域内に形成された第一導電型ソース領域と、第
一導電型ドリフト領域と第一導電型ソース領域とに挟ま
れた第二導電型ウェル領域の表面上に絶縁膜を介して設
けられたゲート電極と、第一導電型ソース領域と第二導
電型ウェル領域との表面に共通に接触するソース電極
と、第一導電型基板の裏面に設けられたドレイン電極と
をもつ縦型ＭＯＳＦＥＴにおいて、第二導電型ウェル領
域の表面から掘り下げられ第一導電型基板近くに達するトレンチと、そのトレンチ内壁に沿って素子耐圧に耐える厚い絶縁膜を介して設けられた導電体とを有し、その
導電体がソース電極と短絡されていることを特徴とする
縦型ＭＯＳＦＥＴ。 | Translation - English
Abstract
Problem: To provide a vertical MOSFET which can markedly reduce on-resistance and is easy to manufacture.
Means for Solving Problem: A vertical MOSFET in which a p-well region 14 is formed in the front surface layer of an n-drift region 12 which is on top of an n -drain layer 11, an n-source region 15 is formed within that p-well region 14, a gate electrode 17 is provided via a gate insulating film 16 on the front surface of the p-well region 14, which is sandwiched between the n-source region 15 and n-drift region 12, and a source electrode 18 which contacts the front surfaces of both the n-source region 15 and p-well region 14 is provided; wherein the impurity concentration distribution of the n-drift region 12 is a linear distribution which gradually increases in the direction of depth, and a trench 22 is dug from the front surface of the p-well region 14, and the inside of the trench 22 is filled with polycrystalline silicon 21 which is shorted to the source electrode via a thick insulating film 20.
WHAT IS CLAIMED IS:
1. A vertical MOSFET including a first conductive drift region of low concentration formed on top of a first conductive substrate of high concentration, a second conductive well region formed selectively in its front surface layer, a first conductive source region formed within said second conductive well region, a gate electrode provided via an insulating film on the front surface of the second conductive well region which is sandwiched between the first conductive drift region and first conductive source region, a source electrode which contacts the front surfaces of both the first conductive source region and second conductive well region, and a drain electrode provided on the rear surface of the first conductive substrate; comprising a trench which is dug from the front surface of the second conductive well region and reaches close to the first conductive substrate, and a conductor provided along the inner walls of said trench via a thick insulating film which withstands the breakdown voltage of the element; wherein said conductor is shorted to the source electrode. |
More Less | | Years of translation experience: 20. Registered at ProZ.com: Feb 2008. Became a member: Mar 2008. | | N/A | | N/A | | NETA | | Microsoft Excel, Microsoft Word, Powerpoint, SDL TRADOS | | CV will be submitted upon request | | About me Lauren has been a professional translator of Japanese documents since 1988. She spent the first 12 years as a full-time freelance translator, and the next 8 years part-time while she worked as a project manager in the software industry. She returned to full-time freelance translation work in March, 2008.
Lauren has extensive experience translating patents and patent litigation-related documents, scientific journal articles and technical specifications. Through translation agencies, major clients have included Motorola, Texas Instruments, General Motors, Smith Klein Beecham and numerous legal firms.
After living in Japan for 1.5 years, Lauren continued her study of Japanese at the Harvard Extension School. In 1988 she was the receipient of a grant from the National Science Foundation to participate in a full-time 8-week course taught at the Massachusetts Institute of Technology titled "Technical Japanese for Scientists and Engineers." The class focused primarily on reading and translation of technical and scientific documents.
Lauren has a degree in Materials Science and Engineering from the Massachusetts Institute of Technology.
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Keywords: Japanese-English, patents, telecom, automotive, electrical, electronics, pharmaceuticals, materials science, materials, chemistry, organic chemistry, semiconductors, electrical engineering
Profile last updated
Oct 21, 2009 |
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