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English to Spanish: Research Article on Fuzzy Logic Controllers - Abstract
Source text - English In this paper, a study on the computational costs of self-tuned fuzzy controllers in several embedded processing architectures is presented. A Takagi - Sugeno system was used as the reference velocity controller of a permanent magnet DC motor, and its response was simulated in Matlab. Such algorithm was then implemented in a PIC18F2550 microcontroller, and a dsPIC30F4011 digital signal processor (DSP), none of which perform floating point operations. In both cases the execution time for a single control cycle was measured, and later compared with the performance characteristics of each processor, putting emphasis on the strategies adopted in order to make the most of such qualities. The same study was repeated afterwards, adding a sel-tunning routine for the controller. The results showed that, when major restrictions in the duration of the control cycle are given, an 8-bits architecture is unable to fulfill the processing requirements of a fuzzy algorithm. The 16-bits architecture's performance was acceptable in this scenario, however, implementing a self-tuning algorithm turned out to be too demanding. It was observed that, for applications with small sampling rates, 8-bits and 16-bits architectures that are not capable of performing floating point operations are not able to run fuzzy algorithms correctly.
Translation - Spanish En este trabajo se presenta un análisis sobre los costes computacionales de la implementación de controladores difusos autoentonados en varias arquitecturas de procesamiento embebido. Se tomó como referencia un controlador Takagi - Sugeno empleado en el control de velocidad de un motor de corriente continua de imán permanente, y se simuló su comportamiento a través de Matlab. Posteriormente se implementó dicho algoritmo en un microcontrolador PIC18F2550 y un DSP dsPIC30F4011, los cuales no poseen procesamiento de valores en punto flotante vía hardware. En ambos casos se midió el tiempo de ejecución de un ciclo de control y se contrastó esta magnitud con las prestaciones de cada núcleo de procesamiento, resaltándose las estrategias empleadas a nivel de código para aprovechar dichas potencialidades. Posteriormente se realizó el mismo estudio, pero esta vez empleando un algoritmo de autoentonación en línea para el controlador. Los resultados demostraron que, para aplicaciones con restricciones significativas en la duración de los ciclos de control, una arquitectura de 8 bits resulta incapaz de cumplir con las demandas de cómputo del algoritmo difuso. La arquitectura DSP de 16 bits resulta viable en estos casos, sin embargo la ejecución de un algoritmo de ajuste en línea resulta demasiado exigente. Se pudo observar que para aplicaciones de control con períodos de muestreo demasiado cortos, las arquitecturas de 8 y 16 bits que no realicen operaciones en punto flotante resultan insuficientes para la correcta ejecución de algoritmos difusos.
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