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interleaving NAND chips in parallel

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11:03 Aug 30, 2008
This question was closed without grading. Reason: Other

English to Chinese translations [PRO]
Tech/Engineering - IT (Information Technology) / solid-state disks
English term or phrase: interleaving NAND chips in parallel
NAND is not efficient at random writes. In fact, most vendors tout burst speeds when offering read and write rates without showing sustained sequential figures in their marketing materials, according to Cohen, Unsworth and others. To make up for this shortcoming, vendors are trying to navigate slow read/write speeds not through the NAND flash itself, but through the controller electronics, memory buffers, multiple controller channels, {interleaving NAND chips in parallel} and flash management software, according to Unsworth.
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