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MEMS wafer capping

French translation: coiffage de tranche (wafer) mems

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GLOSSARY ENTRY (DERIVED FROM QUESTION BELOW)
English term or phrase:MEMS wafer capping
French translation:coiffage de tranche (wafer) mems
Entered by: Alexandre Tissot
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11:11 Aug 28, 2014
English to French translations [PRO]
Tech/Engineering - Engineering (general)
English term or phrase: MEMS wafer capping
Bonjour,

Auriez-vous des idées pour traduire cette expression technique ?

"The XXX Cleanroom Series is ideal for dispensing processes that are often done in a cleanroom such as wafer-level underfill dispensing, 3D packaging, chip encapsulation, dam and fill, dispensing thermal compounds, and ***MEMS wafer capping***."

"bouchage de plaquettes MEMS" ? (pas très convaincu et trop littéral à mon goût)

Merci pour votre aide précieuse.
Alexandre Tissot
Local time: 09:13
coiffage de tranche (wafer) mems
Explanation:
What is capping?

Packaging-compatible wafer level capping of MEMS devices
:
MEMS device is protected with sacrificial material during lead frame packaging and released in the final step. ► MEMS device is released after epoxy encapsulation structure is complete.
http://www.sciencedirect.com/science/article/pii/S0167931712...

SEALING DISPENSING FOR MEMS WAFER CAPPING
:
Wafer capping provides MEMS structure protection after release duringthe dicing process. A cavity wafer covers the MEMS structureby bonding the cavity wafer to the MEMS die wafer,and the two bonded wafers are diced together. In addition wafer capping can provide a vacuum or low pressure with the right material,and a hermetic or almost hermetic seal can be realized
http://www.nordson.com/en-us/divisions/asymtek/support/Libra...

Integrated circuits are passivated from environmental influences by deposited layers of selected materials on the top of the wafer. This is not possible with MEMS since the structures need to remain movable. In MEMS the passivation is achieved by bonding a second wafer to the MEMS wafer. This wafer is called the cap or the capping wafer. We are the pioneer in producing capping wafers with extremely tight dimensional control and low parasitic loads to the small capacitive signals.
http://www.muratamems.fi/en/about-murata/murata-electronics-...

coiffage
n. capping [Tech.]
http://dictionnaire.reverso.net/anglais-francais/capping

Mems capping method and apparatus
:
A MEMS capping method and apparatus uses a cap structure on which is formed a MEMS cavity, a cut capture cavity, and a cap wall. The cap wall is essentially the outer wall of the MEMS cavity and the inner wall of the cut capture cavity. The cap structure is bonded onto a MEMS structure such that the MEMS cavity covers protected MEMS components. The cap structure is trimmed by cutting through to the cut capture cavity from the top of the cap structure without cutting all the way through to the MEMS structure.
http://www.google.com.ar/patents/WO2004003965A3?cl=en&hl=de
Procede et dispositif de coiffage de mems
Cette invention concerne un procédé et un dispositif d'encapsulage pour systèmes électromicromécaniques (MEMS) reposant sur l'emploi d'une structure à coiffe sur laquelle est formée une cavité de réception découpée et une paroi de coiffe. La paroi de chapeau est essentiellement la paroi extérieure de la cavité MEMS et la paroi intérieure de la cavité de réception découpée. La structure de coiffe est collée sur la structure MEMS de telle sorte que la cavité MEMS recouvre les composants MEMS protégés. Pour l'ébavurage de la structure de coiffe, on coupe à travers la cavité de réception depuis le haut de ladite structure de coiffe, sans couper de part en part jusqu'à la structure MEMS.
http://www.google.com.ar/patents/WO2004003965A3?cl=fr&hl=de

Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
:
After introduction and/or application of the anti-stiction fluid, the anti-stiction channel may be sealed, capped, plugged and/or closed to define and control the mechanical damping environment within the chamber. In this regard, sealing, capping and/or closing the chamber establishes the environment within the chamber containing and/or housing the mechanical structures.
http://www.google.kz/patents/EP1683199A2?cl=en&hl=de
Technique anti-frottement au demarrage pour systemes microelectromecaniques encapsules et lies dans des films minces et dans des plaquettes
:
Après introduction et/ou application du fluide anti-frottement au démarrage, le canal anti-frottement au démarrage peut être rendu étanche, coiffé, bouché et/ou fermé pour définir et commander l'environnement d'amortissement mécanique dans la chambre. A cet égard, l'étanchéification, le coiffage et/ou la fermeture de la chambre permet d'établir l'environnement dans la chambre contenant et/ou recevant les structures mécaniques
http://www.google.kz/patents/EP1683199A2?cl=fr&hl=de

Domain Electronics and electrical engineering, Earth sciences
en
Term wafering
Reliability 3 (Reliable)
Term Ref. Pulfrey/29,126,128
Term Note SOLAR ENERGY-PHOTOVOLTAIC CONVERSION
Term wafer slicing
Reliability 3 (Reliable)
Term Ref. Pulfrey/29,126,128
fr
Term découpage en plaques
Reliability 3 (Reliable)
Term découpage en tranches
Reliability 3 (Reliable)
Term Ref. Semiconduct.3842
Term Note ENERGIE SOLAIRE-CONVERSION PHOTOVOLTAIQUE;Cf.:"wafer"(No 2544)
http://iate.europa.eu/SearchByQuery.do?method=searchDetail&l...

Domain Electronics and electrical engineering
en
Definition large single crystal of semiconductor [ IATE:1373573 ], usually silicon, that is used as the substrate [ IATE:1611758 ] on which integrated circuits are manufactured
Definition Ref. J. Daintith and E. Wright, Oxford Dictionary of Computing (6th ed.) (Oxford: Oxford University Press, 2008), http://www.oxfordreference.c... [24.5.2013]
Note In the semiconductor industry, the production of microcircuits involves many steps. The wafer fabrication process typically builds these microcircuits on silicon wafers, and there are many microcircuits per wafer.
Source: http://www-inst.eecs.berkele... [24.5.2013]
Term wafer
Reliability 3 (Reliable)
Context (1) “The idea of putting complete electronic subsystems on a wafer has always had great appeal. The potential advantages of WSI are significant:
• Lower cost per function because of very high levels of integration
• Increased electrical performance through smaller interconnection lengths
• Decreased signal delays by means of circuit densification
• Greater reliability because of decreased interconnections of dissimilar materials…”
(2) "Methods are provided for separating microcircuit dies from a wafer, which includes microcircuit dies containing componentry on a circuit side thereof and streets separating the dies from each other..."
Term Note May also be referred to as a slice [ IATE:1555906 ] or substrate [ IATE:1611758 ].
See: http://en.wikipedia.org/wiki/Wafer_(electronics)#cite_note-1 [24.5.2013]
fr
Term tranche
Reliability 3 (Reliable)
Term Ref. Semiconduttori Diz Int(F Angeli 1971)
Term pastille
Reliability 3 (Reliable)
Term Ref. Semiconduttori Diz Int(F Angeli 1971)
http://iate.europa.eu/SearchByQuery.do?method=searchDetail&l...

Area
Semiconductor devices and integrated circuits / General terms for semiconductor devices
IEV ref
521-05-29
en
wafer
slice or a flat disc, either of semiconductor material or of such a material deposited on a substrate, in which one or more circuits or devices can be processed
fr
tranche, f
plaquette, f
disque de faible épaisseur constitué d'un matériau semiconducteur ou d'un tel matériau déposé sur un substrat, dans lequel un ou plusieurs circuits ou dispositifs peuvent être réalisés
http://www.electropedia.org/iev/iev.nsf/display?openform&iev...

En électronique et micro-électronique, un wafer (de l'anglais) est une tranche, une galette ou une plaque de semi-conducteur.
http://fr.wikipedia.org/wiki/Wafer
Selected response from:

Johannes Gleim
Local time: 09:13
Grading comment
Merci à tous !
4 KudoZ points were awarded for this answer

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Summary of answers provided
4coiffage de tranche (wafer) mems
Johannes Gleim
4couche de revêtement/d'encapsulation sur les galettes intégrant les MEMS
FX Fraipont
Summary of reference entries provided
WAFER in the French!
kashew

  

Answers


1 hr   confidence: Answerer confidence 4/5Answerer confidence 4/5
mems wafer capping
couche de revêtement/d'encapsulation sur les galettes intégrant les MEMS


Explanation:
(systèmes microélectromécaniques)

"Wafer level encapsulation technology for MEMS devices using an HF-permeable PECVD SiOC capping layer
"GJA Verheijden, GEJ Koops, KL Phan… - … , 2008. MEMS 2008. …, 2008 - ieeexplore.ieee.org
ABSTRACT In this paper, a novel technology for the encapsulation of MEMS devices using a
porous capping material is presented. The capping material consists of a low temperature
PECVD layer of SiOC and is shown to be permeable to HF-vapor and H2O and therefore ..."http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=444377...

"Au cours des années 80, l’utilisation des procédés de gravure du silicium développés pour l’industrie microélectronique a permis de fabriquer les premiers dispositifs contenant des micro-éléments mobiles intégrés sur une galette de silicium. Ces nouveaux types de dispositifs appelés MEMS (Micro Electro Mechanical Systems) ont donné naissance à des applications industrielles, particulièrement dans le cadre des capteurs de pression et des têtes d’imprimantes."
http://www.elveflow.com/fr/la-microfluidique-et-les-puces-mi...



FX Fraipont
Belgium
Local time: 09:13
Works in field
Native speaker of: Native in FrenchFrench
PRO pts in category: 1935
Notes to answerer
Asker: Merci, FX.

Login to enter a peer comment (or grade)

6 hrs   confidence: Answerer confidence 4/5Answerer confidence 4/5
mems wafer capping
coiffage de tranche (wafer) mems


Explanation:
What is capping?

Packaging-compatible wafer level capping of MEMS devices
:
MEMS device is protected with sacrificial material during lead frame packaging and released in the final step. ► MEMS device is released after epoxy encapsulation structure is complete.
http://www.sciencedirect.com/science/article/pii/S0167931712...

SEALING DISPENSING FOR MEMS WAFER CAPPING
:
Wafer capping provides MEMS structure protection after release duringthe dicing process. A cavity wafer covers the MEMS structureby bonding the cavity wafer to the MEMS die wafer,and the two bonded wafers are diced together. In addition wafer capping can provide a vacuum or low pressure with the right material,and a hermetic or almost hermetic seal can be realized
http://www.nordson.com/en-us/divisions/asymtek/support/Libra...

Integrated circuits are passivated from environmental influences by deposited layers of selected materials on the top of the wafer. This is not possible with MEMS since the structures need to remain movable. In MEMS the passivation is achieved by bonding a second wafer to the MEMS wafer. This wafer is called the cap or the capping wafer. We are the pioneer in producing capping wafers with extremely tight dimensional control and low parasitic loads to the small capacitive signals.
http://www.muratamems.fi/en/about-murata/murata-electronics-...

coiffage
n. capping [Tech.]
http://dictionnaire.reverso.net/anglais-francais/capping

Mems capping method and apparatus
:
A MEMS capping method and apparatus uses a cap structure on which is formed a MEMS cavity, a cut capture cavity, and a cap wall. The cap wall is essentially the outer wall of the MEMS cavity and the inner wall of the cut capture cavity. The cap structure is bonded onto a MEMS structure such that the MEMS cavity covers protected MEMS components. The cap structure is trimmed by cutting through to the cut capture cavity from the top of the cap structure without cutting all the way through to the MEMS structure.
http://www.google.com.ar/patents/WO2004003965A3?cl=en&hl=de
Procede et dispositif de coiffage de mems
Cette invention concerne un procédé et un dispositif d'encapsulage pour systèmes électromicromécaniques (MEMS) reposant sur l'emploi d'une structure à coiffe sur laquelle est formée une cavité de réception découpée et une paroi de coiffe. La paroi de chapeau est essentiellement la paroi extérieure de la cavité MEMS et la paroi intérieure de la cavité de réception découpée. La structure de coiffe est collée sur la structure MEMS de telle sorte que la cavité MEMS recouvre les composants MEMS protégés. Pour l'ébavurage de la structure de coiffe, on coupe à travers la cavité de réception depuis le haut de ladite structure de coiffe, sans couper de part en part jusqu'à la structure MEMS.
http://www.google.com.ar/patents/WO2004003965A3?cl=fr&hl=de

Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
:
After introduction and/or application of the anti-stiction fluid, the anti-stiction channel may be sealed, capped, plugged and/or closed to define and control the mechanical damping environment within the chamber. In this regard, sealing, capping and/or closing the chamber establishes the environment within the chamber containing and/or housing the mechanical structures.
http://www.google.kz/patents/EP1683199A2?cl=en&hl=de
Technique anti-frottement au demarrage pour systemes microelectromecaniques encapsules et lies dans des films minces et dans des plaquettes
:
Après introduction et/ou application du fluide anti-frottement au démarrage, le canal anti-frottement au démarrage peut être rendu étanche, coiffé, bouché et/ou fermé pour définir et commander l'environnement d'amortissement mécanique dans la chambre. A cet égard, l'étanchéification, le coiffage et/ou la fermeture de la chambre permet d'établir l'environnement dans la chambre contenant et/ou recevant les structures mécaniques
http://www.google.kz/patents/EP1683199A2?cl=fr&hl=de

Domain Electronics and electrical engineering, Earth sciences
en
Term wafering
Reliability 3 (Reliable)
Term Ref. Pulfrey/29,126,128
Term Note SOLAR ENERGY-PHOTOVOLTAIC CONVERSION
Term wafer slicing
Reliability 3 (Reliable)
Term Ref. Pulfrey/29,126,128
fr
Term découpage en plaques
Reliability 3 (Reliable)
Term découpage en tranches
Reliability 3 (Reliable)
Term Ref. Semiconduct.3842
Term Note ENERGIE SOLAIRE-CONVERSION PHOTOVOLTAIQUE;Cf.:"wafer"(No 2544)
http://iate.europa.eu/SearchByQuery.do?method=searchDetail&l...

Domain Electronics and electrical engineering
en
Definition large single crystal of semiconductor [ IATE:1373573 ], usually silicon, that is used as the substrate [ IATE:1611758 ] on which integrated circuits are manufactured
Definition Ref. J. Daintith and E. Wright, Oxford Dictionary of Computing (6th ed.) (Oxford: Oxford University Press, 2008), http://www.oxfordreference.c... [24.5.2013]
Note In the semiconductor industry, the production of microcircuits involves many steps. The wafer fabrication process typically builds these microcircuits on silicon wafers, and there are many microcircuits per wafer.
Source: http://www-inst.eecs.berkele... [24.5.2013]
Term wafer
Reliability 3 (Reliable)
Context (1) “The idea of putting complete electronic subsystems on a wafer has always had great appeal. The potential advantages of WSI are significant:
• Lower cost per function because of very high levels of integration
• Increased electrical performance through smaller interconnection lengths
• Decreased signal delays by means of circuit densification
• Greater reliability because of decreased interconnections of dissimilar materials…”
(2) "Methods are provided for separating microcircuit dies from a wafer, which includes microcircuit dies containing componentry on a circuit side thereof and streets separating the dies from each other..."
Term Note May also be referred to as a slice [ IATE:1555906 ] or substrate [ IATE:1611758 ].
See: http://en.wikipedia.org/wiki/Wafer_(electronics)#cite_note-1 [24.5.2013]
fr
Term tranche
Reliability 3 (Reliable)
Term Ref. Semiconduttori Diz Int(F Angeli 1971)
Term pastille
Reliability 3 (Reliable)
Term Ref. Semiconduttori Diz Int(F Angeli 1971)
http://iate.europa.eu/SearchByQuery.do?method=searchDetail&l...

Area
Semiconductor devices and integrated circuits / General terms for semiconductor devices
IEV ref
521-05-29
en
wafer
slice or a flat disc, either of semiconductor material or of such a material deposited on a substrate, in which one or more circuits or devices can be processed
fr
tranche, f
plaquette, f
disque de faible épaisseur constitué d'un matériau semiconducteur ou d'un tel matériau déposé sur un substrat, dans lequel un ou plusieurs circuits ou dispositifs peuvent être réalisés
http://www.electropedia.org/iev/iev.nsf/display?openform&iev...

En électronique et micro-électronique, un wafer (de l'anglais) est une tranche, une galette ou une plaque de semi-conducteur.
http://fr.wikipedia.org/wiki/Wafer

Johannes Gleim
Local time: 09:13
Specializes in field
Native speaker of: Native in GermanGerman
PRO pts in category: 94
Grading comment
Merci à tous !
Notes to answerer
Asker: Merci, Johannes.

Login to enter a peer comment (or grade)




Reference comments


2 hrs
Reference: WAFER in the French!

Reference information:
http://fr.wikipedia.org/wiki/Wafer

kashew
France
Native speaker of: Native in EnglishEnglish
PRO pts in category: 211
Note to reference poster
Asker: Merci, Kashew.

Login to enter a peer comment (or grade)




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