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HITM#

French translation: HITM#

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GLOSSARY ENTRY (DERIVED FROM QUESTION BELOW)
English term or phrase:HITM#
French translation:HITM#
Entered by: Paul Berthelot
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13:10 Dec 19, 2003
English to French translations [PRO]
Tech/Engineering
English term or phrase: HITM#
test de traduction
électronique
The method according to claim 3, wherein said first control line is a HITM# control line
Paul Berthelot
Local time: 05:01
HITM# (leave as is)
Explanation:
Dans les systèmes à plusieurs mémoires cache, il s'agit de la correspondance (HIT) d'une ligne modifiée (M) dans la mémoire cache de données lors d'un cycle d'interrogation lancé par le système dans le but de vérifier la cohérence des données de cette mémoire cache

Inquire Cycles
In systems with multiple caching masters, external logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus, and then driving EADS#, INV and an inquire address. Such bus cycles cause the processor to compare the physical tags for both its instruction and data caches with the inquire address. If the compare hits a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. If the compare hits a modified line in the data cache, the processor asserts HITM#.
Selected response from:

toubabou
Local time: 23:01
Grading comment
Merci et Meilleurs voeux.
Paul
4 KudoZ points were awarded for this answer

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Summary of answers provided
4HITM# (leave as is)toubabou
1lié au HITM pinAlbert Golub


  

Answers


41 mins   confidence: Answerer confidence 1/5Answerer confidence 1/5
lié au HITM pin


Explanation:
une piste
bonne chance

Albert Golub
Local time: 05:01
Native speaker of: French
PRO pts in pair: 2094

Peer comments on this answer (and responses from the answerer)
neutral  toubabou: what is HITM pin?
2 hrs
Login to enter a peer comment (or grade)

3 hrs   confidence: Answerer confidence 4/5Answerer confidence 4/5
hitm#
HITM# (leave as is)


Explanation:
Dans les systèmes à plusieurs mémoires cache, il s'agit de la correspondance (HIT) d'une ligne modifiée (M) dans la mémoire cache de données lors d'un cycle d'interrogation lancé par le système dans le but de vérifier la cohérence des données de cette mémoire cache

Inquire Cycles
In systems with multiple caching masters, external logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus, and then driving EADS#, INV and an inquire address. Such bus cycles cause the processor to compare the physical tags for both its instruction and data caches with the inquire address. If the compare hits a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. If the compare hits a modified line in the data cache, the processor asserts HITM#.



    Reference: http://www.warthman.com/ex-inqr.htm
toubabou
Local time: 23:01
Native speaker of: Native in FrenchFrench
PRO pts in pair: 756
Grading comment
Merci et Meilleurs voeux.
Paul
Login to enter a peer comment (or grade)




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