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colpi di clock

English translation: clock cycles

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GLOSSARY ENTRY (DERIVED FROM QUESTION BELOW)
Italian term or phrase:colpi di clock
English translation:clock cycles
Entered by: Alexander Chisholm
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09:26 Dec 2, 2003
Italian to English translations [PRO]
Tech/Engineering - IT (Information Technology) / Information technology
Italian term or phrase: colpi di clock
"Inoltre, si supponga che, a meno del segnale di WAIT, il dispositivo di controllo sia stato impostato in modo da considerare un tempo di accesso preimpostato pari a due colpi di clock e, ad esempio, pari complessivamente a 20 ns."

I suppose "clock strokes" is obviously a reasonable translation, but considering the IT context, should the translation be "clock cycles"? Or something else?
Alexander Chisholm
Local time: 22:34
two clock cycles/two clock periods
Explanation:
See examples:

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

*****

Tcl determines which clock edge is access time measured from in SDRAM.
As indicated in Figure 4, Cas latency =3 means the access time Tac is measured from the 2nd clock edge after the "Read" command. All these parameters, Trp, Trcd and Tcl are expressed in number of clock cycles. If you have heard about a 2-2-2 100Mhz SDRAM, it is telling you the SDRAM can work at 100Mhz with Trp, Trcd and Tcl all equals to two clock cycles.

******

The write cycle can be performed in 125 nsec, assuming one wait state and one hold state. The address
setup time of 5 nsec is provided by the SH7615, because the assertion of the WE0# signal is delayed from
the address bus by one-half of a clock period (16 nsec).
The data setup and hold times of the NET2270 are easily met, since the data is presented at least two clock
periods before WE0# is de-asserted, and is held for at least 1 clock period after WE0# is de-asserted. The
IOW# pulse wide requirement of 5 nsec is provided by the SH7615, since it drives WE0# for two clock
periods.








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Note added at 2003-12-02 09:33:20 (GMT)
--------------------------------------------------

\"two clock cycles\": 4070 hits on Google
\"two clock periods\": 456
Selected response from:

Mirella Soffio
Italy
Local time: 22:34
Grading comment
Many thanks to all who answered.
4 KudoZ points were awarded for this answer

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Summary of answers provided
5vedi commenti
Elena Ghetti
4 +1clock ticks
Maurizio Valente
4clock cycles
gianfranco
3two clock cycles/two clock periods
Mirella Soffio


  

Answers


4 mins   confidence: Answerer confidence 3/5Answerer confidence 3/5
two clock cycles/two clock periods


Explanation:
See examples:

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

*****

Tcl determines which clock edge is access time measured from in SDRAM.
As indicated in Figure 4, Cas latency =3 means the access time Tac is measured from the 2nd clock edge after the "Read" command. All these parameters, Trp, Trcd and Tcl are expressed in number of clock cycles. If you have heard about a 2-2-2 100Mhz SDRAM, it is telling you the SDRAM can work at 100Mhz with Trp, Trcd and Tcl all equals to two clock cycles.

******

The write cycle can be performed in 125 nsec, assuming one wait state and one hold state. The address
setup time of 5 nsec is provided by the SH7615, because the assertion of the WE0# signal is delayed from
the address bus by one-half of a clock period (16 nsec).
The data setup and hold times of the NET2270 are easily met, since the data is presented at least two clock
periods before WE0# is de-asserted, and is held for at least 1 clock period after WE0# is de-asserted. The
IOW# pulse wide requirement of 5 nsec is provided by the SH7615, since it drives WE0# for two clock
periods.








--------------------------------------------------
Note added at 2003-12-02 09:33:20 (GMT)
--------------------------------------------------

\"two clock cycles\": 4070 hits on Google
\"two clock periods\": 456

Mirella Soffio
Italy
Local time: 22:34
Native speaker of: Native in ItalianItalian
PRO pts in category: 8
Grading comment
Many thanks to all who answered.
Login to enter a peer comment (or grade)

5 mins   confidence: Answerer confidence 4/5Answerer confidence 4/5
clock cycles


Explanation:
Non ho mai visto "colpi di clock", sono d'accordo con una la tua traduzione "clock cycles"

ciao
Gianfranco


gianfranco
Brazil
Local time: 19:34
Specializes in field
Native speaker of: Native in ItalianItalian
PRO pts in category: 19
Login to enter a peer comment (or grade)

9 mins   confidence: Answerer confidence 4/5Answerer confidence 4/5 peer agreement (net): +1
clock ticks


Explanation:
*

Maurizio Valente
Italy
Native speaker of: Italian
PRO pts in category: 4

Peer comments on this answer (and responses from the answerer)
agree  Francesco Volpe: sì'
4 hrs
Login to enter a peer comment (or grade)

1 hr   confidence: Answerer confidence 5/5
vedi commenti


Explanation:
volevo solo segnalarti questo URL

"These discrete time events are called ticks, clock ticks, clock periods, clocks, cycles, or clock cycles"

perciò sembra che abbiano tutti ragione :-)

www.se.cuhk.edu.hk/~seg3460/tutorial/tut_2supp.pdf

inoltre, trattandosi di un tutorial, forse puoi trovarsi qualche altra parola che ti serve

ciao

Elena Ghetti
Italy
Local time: 22:34
Specializes in field
Native speaker of: Native in ItalianItalian
PRO pts in category: 4
Login to enter a peer comment (or grade)




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