See examples:

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

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Tcl determines which clock edge is access time measured from in SDRAM.
As indicated in Figure 4, Cas latency =3 means the access time Tac is measured from the 2nd clock edge after the "Read" command. All these parameters, Trp, Trcd and Tcl are expressed in number of clock cycles. If you have heard about a 2-2-2 100Mhz SDRAM, it is telling you the SDRAM can work at 100Mhz with Trp, Trcd and Tcl all equals to two clock cycles.

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The write cycle can be performed in 125 nsec, assuming one wait state and one hold state. The address
setup time of 5 nsec is provided by the SH7615, because the assertion of the WE0# signal is delayed from
the address bus by one-half of a clock period (16 nsec).
The data setup and hold times of the NET2270 are easily met, since the data is presented at least two clock
periods before WE0# is de-asserted, and is held for at least 1 clock period after WE0# is de-asserted. The
IOW# pulse wide requirement of 5 nsec is provided by the SH7615, since it drives WE0# for two clock
periods.








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Note added at 2003-12-02 09:33:20 (GMT)
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